如何用VHDL语言编写数码管的动态显示

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity led is
port(
clk:in std_logic;--------------------------------时钟信号
s:out std_logic_vector(7 downto 0);--------------数码管
q:out std_logic_vector(6 downto 0));-------------段位
end led;

architecture one of led is
signal clk1:std_logic;
signal clk2:std_logic;---------------分频

signal cnt:integer:=0;
signal cnt1:integer:=0;---------------计数
signal cnt2:integer:=0;

signal count1:integer:=0;
signal count2:integer:=0;
signal data:integer range 0 to 9;
begin
process(clk)
begin
if clk'event and clk = '1' then
if count1 = 49999999 then
clk1 <= '1';-------------------------------------1 s,以便好计算
count1 <= 0;
else
count1 <= count1+1;
clk1 <= '0';
end if;
if count2 = 50000 then
clk2 <= '1';-------------------------------------1000hz，此频率可利用人的视觉误差扫描数码管
count2 <= 0;
else
count2 <= count2+1;
clk2 <= '0';
end if;
end if;
end process;