请教 VHDL高手。。帮忙编一程序。感激不尽

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------
entity exp18 is
port( Clk : in std_logic; --时钟输入
Rst : in std_logic; --复位输入
R1,R2 : out std_logic; --红灯输出
Y1,Y2 : out std_logic; --黄灯输出
G1,G2 : out std_logic; --绿灯输出
Display : out std_logic_vector(7 downto 0); --七段码管显示输出
SEG_SEL : buffer std_logic_vector(2 downto 0) --七段码管扫描驱动
);
end exp18;
--------------------------------------------------------------------
architecture behave of exp18 is
signal Disp_Temp : integer range 0 to 15;
signal Disp_Decode : std_logic_vector(7 downto 0);
signal SEC1,SEC10 : integer range 0 to 9;
signal Direction : integer range 0 to 15;

signal Clk_Count1 : std_logic_vector(9 downto 0); --产生0.5Hz时钟的分频计数器
signal Clk1Hz : std_logic;
signal Dir_Flag : std_logic; --方向标志

begin
process(Clk)
begin
if(Clk'event and Clk='1') then
if(Clk_Count1<1000) then
Clk_Count1<=Clk_Count1+1;
else
Clk_Count1<="0000000001";
end if;
end if;
end process;
Clk1Hz<=Clk_Count1(9);
process(Clk1Hz,Rst)
begin
if(Rst='0') then
SEC1<=0;
SEC10<=2;
Dir_Flag<='0';
elsif(Clk1Hz'event and Clk1Hz='1') then
if(SEC1=0) then
SEC1<=9;
if(SEC10=0) then
SEC10<=1;
else
SEC10<=SEC10-1;
end if;
else
SEC1<=SEC1-1;
end if;
if(SEC1=0 and SEC10=0) then
Dir_Flag<=not Dir_Flag;
end if;
end if;
end process;

process(Clk1Hz,Rst)
begin
if(Rst='0') then
R1<='1';
G1<='0';
R2<='1';
G2<='0';
else --正常运行
if(SEC10>0 or SEC1>3) then
if(Dir_Flag='0') then --横向通行
R1<='0';
G1<='1';
R2<='1';
G2<='0';
else
R1<='1';
G1<='0';
R2<='0';
G2<='1';
end if;
else
if(Dir_Flag='0') then --横向通行
R1<='0';
G1<='0';
R2<='1';
G2<='0';
else
R1<='1';
G1<='0';
R2<='0';
G2<='0';
end if;
end if;
end if;
end process;

process(Clk1Hz)
begin
if(SEC10>0 or SEC1>3) then
Y1<='0';
Y2<='0';
elsif(Dir_Flag='0') then
Y1<=Clk1Hz;
Y2<='0';
else
Y1<='0';
Y2<=Clk1Hz;
end if;
end process;

process(Dir_Flag)
begin
if(Dir_Flag='0') then --横向
Direction<=10;
else --纵向
Direction<=11;
end if;
end process;

process(SEG_SEL)
begin
case (SEG_SEL+1) is
when "000"=>Disp_Temp<=Direction;
when "001"=>Disp_Temp<=Direction;
when "010"=>Disp_Temp<=SEC10;
when "011"=>Disp_Temp<=SEC1;
when "100"=>Disp_Temp<=Direction;
when "101"=>Disp_Temp<=Direction;
when "110"=>Disp_Temp<=SEC10;
when "111"=>Disp_Temp<=SEC1;
end case;
end process;

process(Clk)
begin
if(Clk'event and Clk='1') then --扫描累加
SEG_SEL<=SEG_SEL+1;
Display<=Disp_Decode;
end if;
end process;
process(Disp_Temp) --显示转换
begin
case Disp_Temp is
when 0=>Disp_Decode<="00111111"; --'0'
when 1=>Disp_Decode<="00000110"; --'1'
when 2=>Disp_Decode<="01011011"; --'2'
when 3=>Disp_Decode<="01001111"; --'3'
when 4=>Disp_Decode<="01100110"; --'4'
when 5=>Disp_Decode<="01101101"; --'5'
when 6=>Disp_Decode<="01111101"; --'6'
when 7=>Disp_Decode<="00000111"; --'7'
when 8=>Disp_Decode<="01111111"; --'8'
when 9=>Disp_Decode<="01101111"; --'9'
when 10=>Disp_Decode<="01001000"; --'='
when 11=>Disp_Decode<="00010100"; --'||'
when others=>Disp_Decode<="00000000"; --全灭
end case;
end process;

end behave;
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分不是问题^_^
助人为乐！认真看下代码，对你有好处的^_^
另外调试有问题在我空间里留言，我定期会去看。
此外注意管脚定义