FPGA：谁有vhdl语言的I⼀O复用ram程序啊，就是输入输出用相同端口的,求程序！

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
ENTITY sram IS
GENERIC(addr_length:Positive:=5;
bit_wide:Positive:=8);
PORT(wr,rd:IN std_logic;
address:IN std_logic_vector(addr_length-1 DOWNTO 0);
data:INOUT std_logic_vector(bit_wide-1 DOWNTO 0));
END sram;
ARCHITECTURE behavioral OF sram IS
TYPE memory IS ARRAY(addr_length-1 DOWNTO 0) OF std_logic_vector(bit_wide-1 DOWNTO 0);
BEGIN
PROCESS(wr,rd,address,data)
VARIABLE mem:memory;
BEGIN
IF wr='0' AND rd='1' THEN
data <= (OTHERS => 'Z');
mem(conv_integer(address)) := data;
ELSIF wr='1' AND rd='0' THEN
data <= mem(conv_integer(address));
END IF;
END PROCESS;
END behavioral;