求eda数字钟设计程序

1.Topclock（元件例化 顶层文件）
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;
Entity topclock is
Port(clk,clr,en,m1,h1:in std_logic;
alarm:out std_logic;
secs,secg,mins,ming,hours,hourg:buffer std_logic_vector(3 downto 0));
End;
2. 秒模块程序
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity SECOND is
port(clk,clr:in std_logic;
sec1,sec0:out std_logic_vector(3 downto 0);
co:out std_logic);
end SECOND;

architecture SEC of SECOND is
begin
process(clk,clr)
variable cnt1,cnt0:std_logic_vector(3 downto 0);
begin
if clr='1' then
cnt1:="0000";
cnt0:="0000";
elsif clk'event and clk='1' then
if cnt1="0101" and cnt0="1000" then
co<='1';
cnt0:="1001";
elsif cnt0<"1001" then
cnt0:=cnt0+1;
else
cnt0:="0000";

if cnt1<"0101" then
cnt1:=cnt1+1;
else
cnt1:="0000";
co<='0';
end if;
end if;
end if;
sec1<=cnt1;
sec0<=cnt0;

end process;
end SEC;

3.分模块程序
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity MINUTE is
port(clk,en:in std_logic;
min1,min0:out std_logic_vector(3 downto 0);
co:out std_logic);
end MINUTE;

architecture MIN of MINUTE is
begin
process(clk)
variable cnt1,cnt0:std_logic_vector(3 downto 0);
begin
if clk'event and clk='1' then
if en='1' then
if cnt1="0101" and cnt0="1000" then
co<='1';
cnt0:="1001";
elsif cnt0<"1001" then
cnt0:=cnt0+1;
else
cnt0:="0000";

if cnt1<"0101" then
cnt1:=cnt1+1;
else
cnt1:="0000";
co<='0';
end if;
end if;
end if;
end if;
min1<=cnt1;
min0<=cnt0;

end process;
end MIN;

4.时模块程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity HOUR is
port(clk,en:in std_logic;
h1,h0:out std_logic_vector(3 downto 0));
end HOUR;

architecture hour_arc of HOUR is
begin
process(clk)
variable cnt1,cnt0:std_logic_vector(3 downto 0);
begin
if clk'event and clk='1' then
if en='1' then
if cnt1="0010" and cnt0="0011" then
cnt1:="0000";
cnt0:="0000";
elsif cnt0<"1001" then
cnt0:=cnt0+1;
end if;
end if;
end if;
h1<=cnt1;
h0<=cnt0;

end process;
end hour_arc;

----5.扫描模块程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity SELTIME is
port(
clk:in std_logic;
sec1,sec0,min1,min0,h1,h0:in std_logic_vector(3 downto 0);
daout:out std_logic_vector(3 downto 0);
sel:out std_logic_vector(2 downto 0));
end SELTIME;
architecture fun of SELTIME is
signal count:std_logic_vector(2 downto 0);
begin
sel<=count;
process(clk)
begin
if(clk'event and clk='1') then
if(count>="101") then
count<="000";
else
count<=count+1;
end if;
end if;
case count is
when"000"=>daout<= sec0;
when"001"=>daout<= sec1;
when"010"=>daout<= min0;
when"011"=>daout<= min1;
when"100"=>daout<=h0;
when others =>daout<=h1;
end case;
end process;
end fun;

6.显示模块程序

library ieee;
use ieee.std_logic_1164.all;
entity DISPLAY is
port(d:in std_logic_vector(3 downto 0);
q:out std_logic_vector(6 downto 0));
end DISPLAY;
architecture disp_are of DISPLAY is
begin
process(d)
begin

case d is
when"0000" =>q<="0111111";
when"0001" =>q<="0000110";
when"0010" =>q<="1011011";
when"0011" =>q<="1001111";
when"0100" =>q<="1100110";
when"0101" =>q<="1101101";
when"0110" =>q<="1111101";
when"0111" =>q<="0100111";
when"1000" =>q<="1111111";
when others =>q<="1101111";
end case;
end process;
end disp_are;

-----7.定时闹钟模块程序

library ieee;
use ieee.std_logic_1164.all;
entity ALERT is
port(m1,m0,s1,s0:in std_logic_vector(3 downto 0);
clk:in std_logic;
q500,qlk:out std_logic);
end ALERT;

architecture sss_arc of ALERT is
begin
process(clk)
begin

if clk'event and clk='1' then
if m1="0101" and m0="1001" and s1="0101" then
if s0="0001" or s0="0011" or s0="0101" or s0="0111" then
q500<='1';
else
q500<='0';
end if;
end if;

if m1="0101" and m0="1001" and s1="0101" and s0="1001" then
qlk<='1';
else
qlk<='0';
end if;
end if;
end process;
end sss_arc;
Architecture one of topclock is
Component second1
Port( clks,clr:in std_logic;
secs,secg: buffer std_logic_vector(3 downto 0);
cout1: out std_logic);
End Component;
Component min1
Port(clkm,clr:in std_logic;
mins,ming:buffer std_logic_vector(3 downto 0);
enmin,alarm: out std_logic);
End Component;
Component hour1
Port(clkh,clr:in std_logic;
hours,hourg:buffer std_logic_vector(3 downto 0));
End Component;
Component madapt
Port(en,m1,clk,secin:in std_logic;
minset:out std_logic);
End Component;
Component hadapt
Port(en,h1,clk,minin:in std_logic;
hourset:out std_logic);
End Component;
signal a,b,c,d: std_logic;
begin
u1:second1 port map(clr=>clr,
secs=>secs,secg=>secg,clks=>clk, cout1=>a);
u2:min1 port map(clr=>clr,alarm=>alarm,
mins=>mins,ming=>ming,clkm=>b,enmin=>c);
u3:hour1 port map(clr=>clr,
hours=>hours,hourg=>hourg,clkh=>d);
u4:madapt port map(en=>en,m1=>m1,clk=>clk,secin=>a,minset=>b);
u5:hadapt port map(en=>en,h1=>h1,clk=>clk,minin=>c,hourset=>d);
end;

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ORG 0000H ;程序入口地址
AJMP START
ORG 000BH ;定时器0中断入口地址
LJMP INT_0
ORG 001BH ;定时器1中断入口地址
LJMP INT_1
ORG 0100H
START:LCALL QING ;初始化
QING: ;初始化
MOV 30H,#0 ;时十位寄存器清零
MOV 31H,#0 ;时个位寄存器清零
MOV 32H,#0 ;分十位寄存器清零
MOV 33H,#0 ;分个位寄存器清零
MOV 34H,#0 ;秒十位寄存器清零
MOV 35H,#0 ;秒个位寄存器清零
MOV 36H,#0 ;秒
MOV 37H,#0 ;分
MOV 38H,#0 ;时
MOV 39H,#20
MOV 40H,#0
MOV 41H,#0
MOV TMOD,#11H
MOV TH0,#3CH
MOV TL0,#0B0H ;赋初值，定时50ms
MOV TH1,#09EH
MOV TL1,#0D0H
SETB TR0 ;开启定时器0
SETB TR1
SETB EA ;开中断总开关
SETB ET0 ;定时器0中断允许位
SETB ET1
SETB PT0
CLR PT1

MAIN:MOV P3,#0FFH ;开启按键
JNB P3.3,KEY ;扫描按键
AJMP MAIN
KEY:JNB P3.3,KEY ;控制时钟
MOV 41H,#1
CLR TR0 ;关“T0“中断
LJMP KEY1
DISPLAY: ;数码管
MOV DPTR,#TABLE
MOV P2,#80H
MOV A,35H ; 显示秒个位
MOVC A,@A+DPTR
MOV P0,A
ACALL DELAY

MOV P2,#40H
MOV A,34H ;显示秒十位
MOVC A,@A+DPTR
MOV P0,A
ACALL DELAY

MOV P2,#20H
MOV A,33H ; 显示分个位
MOVC A,@A+DPTR
MOV P0,A
ACALL DELAY

MOV P2,#10H
MOV A,32H ; 显示分十位
MOVC A,@A+DPTR
MOV P0,A
ACALL DELAY

MOV P2,#20H
MOV P0,#7FH ;显示小数点
ACALL DELAY

JNB P3.2,LOOP ;转为” 时分“显示
LJMP EXIT
LOOP:JNB P3.2,LOOP
MOV 40H,#1
AJMP EXIT
DELAY:
MOV R3,#50 ;延时约为50MS
D0:
MOV R2,#50
DJNZ R2,$
DJNZ R3,D0
RET
DISPLAY_1:
MOV P2,#80H
MOV A,33H ; 显示分个位
MOVC A,@A+DPTR
MOV P0,A
ACALL DELAY

MOV P2,#40H
MOV A,32H ; 显示分十位
MOVC A,@A+DPTR
MOV P0,A
ACALL DELAY

MOV P2,#20H
MOV A,31H ;显示时个位
MOVC A,@A+DPTR
MOV P0,A
ACALL DELAY

MOV P2,#10H
MOV A,30H ; 显示时十位
MOVC A,@A+DPTR
MOV P0,A
ACALL DELAY

MOV P2,#20H
MOV P0,#7FH ;显示小数点
ACALL DELAY

JNB P3.2,LOOP1 ;转为”分秒“显示
LJMP EXIT
LOOP1:JNB P3.2,LOOP1
MOV 40H,#0
LJMP EXIT
K3:JNB P3.4,K3
KEY3:JNB P3.5,K2_0 ;调整”时“
JNB P3.3,SHI_0
AJMP KEY3

SHI_0:JNB P3.3,SHI_0
SHI:JNB P3.4,JIA_SHI ;”时“
JNB P3.5,JIAN_SHI
JNB P3.3,KEY0
AJMP SHI
JIA_SHI:JNB P3.4,JIA_SHI ; 加时
INC 36H
MOV R0,36H
CJNE @R0,#24,SHI
MOV 36H,#0
AJMP SHI
JIAN_SHI:JNB P3.5,JIAN_SHI ; 减时
DEC 36H
MOV R0,36H
CJNE @R0,#-1,SHI
MOV 36H,#23
AJMP SHI
KEY0: JNB P3.3,KEY0 ;转为时钟
MOV 41H,#0
MOV TH0,#3CH
MOV TL0,#0B4H
SETB TR0 ;开”T0” 中断
AJMP MAIN

K2: JNB P3.4,K2
K2_0: JNB P3.5,K2_0
KEY2: JNB P3.4,K3 ;调整”分“
JNB P3.5,K1
JNB P3.3,F_0
AJMP KEY2

K1: JNB P3.5,K1
KEY1: ;调整”秒“
JNB P3.4,K2
JNB P3.3,S_0
AJMP KEY1

S_0: JNB P3.3,S_0
S: JNB P3.3,KEY0 ; ”秒“
JNB P3.4,JIA_S
JNB P3.5,JIAN_S
AJMP S
JIA_S:JNB P3.4,JIA_S ;加秒
INC 38H
MOV R0,38H
CJNE @R0,#61,S
MOV 38H,#0
AJMP S
JIAN_S:JNB P3.5,JIAN_S ;减秒
DEC 38H
MOV R0,38H
CJNE @R0,#-1,S
MOV 38H,#59
AJMP S

F_0:JNB P3.3,F_0
F: JNB P3.4,JIA_F ; ”分“
JNB P3.5,JIAN_F
JNB P3.3,KEY0

AJMP F
JIA_F:JNB P3.4,JIA_F ;加 ”分“
INC 37H
MOV R0,37H
CJNE @R0,#60,F
MOV 37H,#0
AJMP F
JIAN_F:JNB P3.5,JIAN_F ;减 ”分“
DEC 37H
MOV R0,37H
CJNE @R0,#-1,F
MOV 37H,#59
AJMP F

INT_0: ;中断0初始化
MOV TH0,#4BH
MOV TL0,#0EAH
DJNZ 39H,EXIT
MOV 39H,#20
MOV A,41H ; 41H控制是否计时
CJNE A,#1,INT_01

INT_01:
INC 38H
MOV A,38H
CJNE A,#60,EXIT
MOV 38H,#0
INC 37H
MOV A,37H
CJNE A,#60,EXIT
MOV 37H,#0
INC 36H
MOV A,36H
CJNE A,#24,EXIT
MOV 36H,#0

INT_1:
MOV TH1,#9EH ;定时1中断
MOV TL1,#0D0H

INT_13: ;数据转换 “时”“分”“秒”
MOV A,36H
MOV B,#10
DIV AB
MOV 30H,A
MOV 31H,B
MOV A,37H
MOV B,#10
DIV AB
MOV 32H,A
MOV 33H,B
MOV A,38H
MOV B,#10
DIV AB
MOV 34H,A
MOV 35H,B
ACALL X1
EXIT:
RETI

X1: MOV A,40H ;分秒转换
CJNE A,#1,X2
LJMP DISPLAY_1
X2: LJMP DISPLAY
RET
TABLE: ;数据调用
DB 0C0H,0F9H,0A4H,0B0H,99H,92H,82H,0F8H,80H,90H ;字形显示编码

END

EDA的数字钟设计

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数字钟功能介绍.

基本功能要求.

扩展功能要求.

总体方案介绍.

计时方案.

键盘/显示方案.

..........
YOU的

设计方案

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