module hz(clk_50,clk_1);
input clk_50;
output clk_1;
reg clk_1;
reg [5:0] cnt;
always@(posedge clk_50)
begin if (cnt==6'd24)
cnt <= 6'd0;
else cnt <= cnt+1;
end
always@(posedge clk_50)
begin if (cnt==6'd0)
clk_1 <= ~clk_1;
end
endmodule
output oCLK;
reg[5:0] rgCnt;
always @(posedge iCLK)
begin
if(rgCnt>=6'd49) rgCnt<=6'd0;
else rgCnt<=rgCnt+1'b1;
end
assign oCLK = (rgCnt<6'd25)? 1'b0 : 1'b1;
50分频即可
内容全部来源于网络收集，如有侵权，请联系网站删除：QQ：24596024