用vhdl语言设计二位全加器

library ieee;
use ieee.std_logic_1164.all;
entity product_adder_subtracter is
port(
a,b:in std_logic_vector(7 downto 0);
s:out std_logic_vector(8 downto 0));
end;
architecture behavioral of product_adder_subtracter is
begin
behavior:process(a,b) is
variable carry_in:std_logic;
variable carry_out:std_logic;
variable op2:std_logic_vector(b'range);
begin
op2:=b;
end if;
for index in 0 to 7 loop
carry_in:=carry_out;
s(index)<=a(index) xor op2(index)xor carry_in ;
carry_out:=(a(index)and op2(index))
or(carry_in and (a(index) xor op2(index)));
end loop;
s(8)<=a(7) xor op2(7) xor carry_out;
end process;
end;

到我宿舍来抄啊，速度点。。。。（望采纳给我加分！！！）不然不给你答案